DC offset in an amplifier may arise from device mismatch within the amplifier. For audio products, a high offset may lead to poor “pop and click” performance. Offset may arise from a number of sources during fabrication of an amplifier. Device areas, current mirrors, threshold voltages, and/or conduction factors may differ in an integrated circuit due to process variations.
Many precision and power amplifiers utilize a trimming process during production to achieve high precision DC offset. However, production trimming may increase process and testing costs for such amplifiers.
Alternatively, matching may be improved by layout techniques (for example, the common centroid technique) and/or by increasing a total area of the input devices. However, with such techniques, a degree of matching typically improves by the square root of the total area. In a typical CMOS process, reducing the maximum offset to millivolt levels may require a large area for the input pair, so much so that this technique may become cost prohibitive. To achieve microvolt offsets, other solutions (such as trimming, binning, or using a BiCMOS process) may also be expensive.